1. Field of the Invention
The present invention relates to a boosting circuit for a high voltage operation in a semiconductor memory device, and in particular to an improved boosting circuit for a high voltage operation which can prevent a transistor of a high voltage pump circuit from being destroyed due to an excessive bootstrap voltage in a pumping operation, by controlling the operation of the high voltage pump circuit according to a signal which detects when the bootstrap voltage of the high voltage pump circuit has increased above a predetermined level.
2. Description of the Background Art
In general, the DRAM is a random access memory for writing or reading data to/from a memory cell having one transistor and one capacitor. When a RAS bar signal /RAS which is a row address strobe signal is activated, the DRAM decodes an inputted row address to drive a selected word line.
Since the cell transistor composing the memory cell uses an NMOS, the DRAM includes a word line driving VPP generator for generating a potential of a power voltage VCC+a threshold voltage Vtn+xcex94V by considering a voltage loss due to the threshold voltage Vtn.
That is, a PMOS transistor successfully transmits a high potential, but it is difficult to transmit a low potential below the threshold voltage. An NMOS transistor successfully transmits a low potential, but it is difficult to transmit a potential higher than a potential which is lower than a gate potential by the threshold voltage. Therefore, when the NMOS transistor is used to decrease a size of the device or prevent a latch-up, a potential higher than a high potential transmitted to a gate of the NMOS transistor by at least the threshold voltage should be applied to successfully transmit the high potential. As a result, the high voltage VPP having a higher potential than the power voltage VCC is required to drive the word line of the DRAM.
FIG. 1 is a block diagram illustrating a conventional boosting circuit for a high voltage operation. Referring to FIG. 1, the conventional boosting circuit includes a VPP level detecting unit 10, a VPP control circuit unit 20, a ring oscillator unit 30 and a VPP pump unit 40.
When an operation control signal BIE indicating that a high voltage operation mode has a high level, the VPP level detecting unit 10 compares the high voltage VPP with a reference voltage Vref, and outputs a signal VPBSB upon detecting that the high voltage VPP has reached a target value. Here, when the high voltage VPP is higher than the reference voltage Vref, the output signal VPBSB has a low level, thus preventing a VPP pumping operation. When the high voltage VPP is lower than the reference voltage Vref, the output signal VPBSB has a high level, thus performing the VPP pumping operation.
The VPP control circuit unit 20 receives the output signal VPBSB from the VPP level detecting unit 10 and the operation control signal BIE, and generates a signal OSCSW for controlling the operation of the ring oscillator unit 30. When the output signal VPBSB from the VPP level detecting unit 10 and the operation control signal BIE have a high level, the VPP control circuit unit 20 generates the high level output signal OSCSW to operate the ring oscillator unit 30. When any of the output signal VPBSB from the VPP level detecting unit 10 and the operation control signal BIE has a low level, the output signal OSCSW has a low level so as not to operate the ring oscillator unit 30.
When the output signal OSCSW from the VPP control circuit unit 20 has a high level, the ring oscillator unit 30 performs an oscillation operation to generate a pulse signal BPOSC having a predetermined period. When the output signal OSCSW from the VPP control circuit unit 20 has a low level, the ring oscillator unit 30 is not operated.
The VPP pump unit 40 pumps electric charges until the VPP voltage reaches the target value according to the pulse signal BPOSC from the ring oscillator unit 30.
That is, in the high voltage operation mode, the operation control signal BIE is enabled in a high level, and the ring oscillator unit 30 starts the operation. The VPP pump unit 40 is operated according to the pulse signal BPOSC from the ring oscillator unit 30, thereby increasing the VPP voltage. Thereafter, the VPP level detecting unit 10 detects the VPP voltage, prevents the VPP pumping operation when the detected value reaches the target value, and facilitates the VPP pumping a operation when the detected value does not reach the target value. By repeating the procedure, the VPP voltage maintains a constant potential.
FIG. 2 is a circuit diagram illustrating the conventional VPP level detecting unit 10 of FIG. 1. The VPP level detecting unit 10 includes: a PMOS transistor P1 connected in a diode structure between the high voltage VPP and a node Nd1; a PMOS transistor P2 being connected between the node Nd1 and a node Nd2, having its gate connected to receive the power voltage VDD, and being turned on when a potential of the node Nd1 is higher than the power voltage VDD; a PMOS transistor P3 connected between the node Nd2 and a node Nd3, and turned on when the operation control signal BIE has a high level, for transmitting the signal of the node Nd2 to the node Nd3; an NMOS transistor N1 connected in a diode structure between the node Nd3 and a ground voltage VSS, and turned on when the signal of the node Nd3 is higher than the threshold voltage Vt, for discharging the voltage of the node Nd3 to the ground voltage VSS; and an NMOS transistor N2 connected between the node Nd3 and the ground voltage VSS, and turned on when the operation control signal BIE has a low level, thereby making the voltage at node Nd4 a high level, for discharging the voltage of the node Nd3 to the ground voltage VSS. In addition, the VPP level detecting unit 10 includes: a PMOS transistor P4 being connected between the power voltage VDD and a node Nd5, and having its gate connected to receive the ground voltage VSS; NMOS transistors N3 and N4 connected in series between the node Nd5 and the ground voltage VSS, and respectively controlled according to the signal of the node Nd3 and the power voltage VDD; and inverters IV1 and IV2 connected in series between the node Nd5 and a node Nd6 outputting an output signal VPBSB.
In the, VPP level detecting unit 10, when the operation control signal BIE has a high level, the PMOS transistor P3 is turned on, and the NMOS transistor N2 is turned off, to transmit xe2x80x98VPPxe2x80x94threshold value Vt of PMOS transistors P1-P3xe2x80x99 to the node Nd3. Here, when the VPP voltage exceeds xe2x80x98power voltage VDD+|2Vtp|xe2x80x99, the output signal VPBSB has a low level, thereby stopping the VPP pumping operation. Vtp denotes the threshold voltage of the PMOS transistors. Conversely, when the VPP voltage is lower than xe2x80x98power voltage VDD+|2Vtp|xe2x80x99, the output signal VPBSB has a high level, thereby performing a boosting operation for pumping the VPP voltage.
FIG. 3 is a circuit diagram illustrating the conventional 40 VPP control circuit unit 20 of FIG. 1. The VPP control circuit unit 20 includes: a NAND gate NA1 for receiving the output signal VPBSB from the VPP level detecting unit 10 and the operation control signal BIE; and inverters IV3-IV5 connected in series between an output node Nd7 of the NAND gate NA1 and an output terminal Nd8 outputting the signal OSCSW.
When the output signal VPBSB from the VPP level detecting unit 10 and the operation control signal BIE have a high level, the VPP control circuit unit 20 generates the high level output signal OSCSW. When the output signal OSCSW has a high level, the ring oscillator unit 30 is operated to pump the VPP voltage.
FIG. 4 is a circuit diagram illustrating the conventional ring oscillator unit 30 of FIG. 1. The ring oscillator unit 30 includes: a NAND gate NA2 for receiving the output signal OSCSW from the VPP control circuit unit 20 and the output signal BPOSC; and inverters IV6-IV9 connected in series between an output node Nd9 of the NAND gate NA2 and an output terminal Ndl0 outputting the signal BPOSC.
When the output signal OSCSW from the VPP control circuit unit 20 has a high level, the ring oscillator unit 30 performs the oscillation operation, thereby generating the pulse signal BPOSC having a predetermined period. When the output signal OSCSW from the VPP control circuit unit 20 has a low level, the ring oscillator unit 30 is not operated.
FIG. 5 is a circuit diagram illustrating the conventional VPP pump unit 40 of FIG. 1. The VPP pump unit 40 includes: an input node Nd11 for receiving the output signal BPOSC from the ring oscillator unit 30; an inverter IV10 for receiving the signal of the node Nd11, and outputting an inverted signal to a node Nd12; inverters IV11-IV13 connected in series between the node Nd12 and a node Nd13; an NMOS transistor N5 having its source and drain commonly connected to the node Nd13, having its gate connected to a node Nd14, and transmitting a bootstrap voltage to the node Nd14; an NMOS transistor N6 connected in a diode structure between the power voltage VDD and the node Nd14; an inverter IV14 connected between the output node Nd12 of the inverter IV10 and a node Nd16; an NMOS transistor N8 having its source and drain commonly connected to the node Nd16, having its gate connected to a node Nd17, and transmitting the bootstrap voltage to the node Nd17; an NMOS transistor N9 connected in a diode structure between the power voltage VDD and the node Nd17; an NMOS transistor N10 having its source and drain commonly connected to the node Nd17, having its gate connected to a node Nd18, and transmitting the bootstrap voltage to the node Nd18; an NMOS transistor N11 connected in a diode structure between the power voltage VDD and the node Nd18; and an NMOS transistor N7 ADD being connected between the node Nd14 and an output terminal Nd15 outputting the VPP voltage, and having its gate connected to receive the signal of the node Nd18.
When the VPP level detecting unit 10 does not exist, the VPP pump unit 40 instantaneously generates a potential of 2VDD according to the pulse signal BPOSC from the ring oscillator unit 30, thereby supplying electric charges to the VPP node.
In the conventional boosting circuit for the high voltage operation, the potential of the node Nd18 transmitted to the gate of the NMOS transistor N7 of the VPP pump unit 40 is maximally xe2x80x983VDD -|2vtn|xe2x80x99, and thus the NMOS transistor N7 may be destroyed. When the power voltage VDD is 5V, the potential of 14V seriously damages the reliability of the NMOS transistor N7.
Accordingly, it is an object of the present invention to provide a boosting circuit for a high voltage operation which can prevent a transistor of a high voltage pump circuit from being destroyed due to an excessive bootstrap voltage in a pumping operation, by controlling the operation of the high voltage pump circuit according to a signal detecting that the bootstrap voltage of the high voltage pump circuit has increased above a predetermined level.
In order to achieve the above-described object of the invention, there is provided a boosting circuit for a high voltage operation, including: a VPP pump unit for boosting a power voltage, and generating a high voltage; a first VPP level detecting unit for comparing the high voltage from the VPP pump unit with a reference voltage according to a high voltage operation signal, and outputting a resulting signal; a second VPP level detecting unit for receiving the highest voltage boosted in the VPP pump unit according to the high voltage operation signal, comparing the highest voltage with the reference voltage, and outputting a resulting signal; a VPP control circuit unit for receiving the output signal from the first VPP level detecting unit, the output signal from the second VPP level detecting unit and the high voltage operation signal, and generating a signal for controlling a VPP pumping operation; and a ring oscillator unit for performing an oscillation operation according to the output signal from the VPP control circuit unit, and generating a pulse signal having a predetermined period for controlling the operation of the VPP pump unit.
The first VPP level detecting unit generates a control signal for preventing the VPP pumping operation when the high voltage is higher than the reference voltage, and generates a control signal for pumping the VPP voltage when the high voltage is lower than the reference voltage.
The second VPP level detecting unit generates a control signal for preventing the VPP pumping operation when the voltage is higher than the reference voltage, and generates a control signal for pumping the VPP voltage when the voltage is lower than the reference voltage.
The VPP control circuit unit generates a signal for operating the ring oscillator unit when the output signal from the first VPP level detecting unit, the output signal from the second VPP level detecting unit and the operation control signal have a high level.
The ring oscillator unit generates a pulse signal having a predetermined period when the output signal from the VPP control circuit unit has a high level.